The present invention relates generally to the field of digital computer systems, and more specifically, to a method for operating a hierarchical translation lookaside buffer.
Recent microprocessor architecture allows software to use “virtual” (or sometimes called “logical”) addresses to reference memory locations. The memory access itself is done using a “physical” (or sometimes called “absolute”) address. To translate between the two, typically a data structure called Translation Lookaside Buffer (TLB) is involved. The process of translating is sometimes called Dynamic Address Translation (DAT), in particular in the IBM z/Architecture.
Entries in a hierarchical TLB are linked via tags. In the hierarchical TLB, entries have a 1:n relationship, e.g. a higher level entry can point to n lower lever entries (for instance a 1M segment can have 2048 4 k pages). However, when new entries are created it has to be ensured in an efficient manner that the links between higher and lower level remain consistent.